In the nonvolatile memory express (NVMe) system, a host device writes data storage device commands, such as read commands, write commands, and administrative commands, in submission queues that are implemented in host memory. The nonvolatile storage device fetches the commands from the submission queues, executes the commands, and posts entries in completion queues, which are also implemented in host memory, to notify the host device of the completion of the commands. The NVMe standard, the current version of which is NVM Express, Revision 1.2, Nov. 3, 2014, the disclosure of which is incorporated herein by reference in its entirety, describes that the nonvolatile storage device posts a completion entry to an appropriate completion queue in the host device via a communication that is typically smaller than the cache line size of the host device memory. Further, each completion entry is posted in the completion queue via a partial cache line write that compels the host device to perform a read-modify-write operation. Notably, such a read-modify-write operation is inefficient as compared to a single write operation than can be used to perform a full cache line write. In addition, the practice of communicating single (i.e., small in data size) write requests to the host device from the data storage device via a connecting peripheral component interconnect express (PCIe) bus is considerably inefficient.
Accordingly, there exists a need for methods, systems, and computer readable media for aggregating completion entries in a nonvolatile storage device.